This solicitation closed on September 23, 2026
View current Department of Defense opportunities →Multi-Core Parallel Processing for Sensor Fusion Architecture
AI Overview
This RFP seeks development of a multi-core parallel processing sensor fusion architecture to eliminate data loss and reduce latency in target tracking for manned and autonomous systems. The modular, platform-agnostic design must integrate multiple sensor types while maintaining real-time performance and compatibility with fifth-generation platforms.
This summary is AI-generated from the official solicitation.
Key Details
Official Description
The enhancement of target tracking, situational awareness, and decision-making in manned and autonomous systems is accomplished by fusing data from multiple sensors (homogeneous and heterogeneous). There are many complex issues within the implementation of sensor fusion, including, but not limited to, process latency, overprocessing of redundant data, and the inherent serial nature of current fusion architecture. To alleviate these issues, a prioritization ranking system is implemented to proces...
Change History
Informational change · Status
Multi-Core Parallel Processing for Sensor Fusion Architecture
Status changed from status: Open to status: Closed.
Informational change · Description
Multi-Core Parallel Processing for Sensor Fusion Architecture
Description information changed.
Multi-Core Parallel Processing for Sensor Fusion Architecture
Key Change:
Q3 received a comprehensive new answer clarifying five critical points: (1) Secret-level facility clearance not required at Phase I award; uncleared firms with sponsorship path are viable; (2) evaluation is holistic—strong architecture/simulation rigor is primary, not just domain experience; (3) establishing serial baseline is Phase I scope, not government-furnished; (4) sub-task decomposition is illustrative, not prescriptive; (5) track integrity proof via deterministic metrics (zero drops, message accounting, latency/throughput bounds, association accuracy).
Multi-Core Parallel Processing for Sensor Fusion Architecture
Changes to Q&A:
Added 2 new questions: Q1 asking if topic supports chip development (answer not provided), and Q2 asking if synthetic multi-sensor track/report streams are acceptable for adapter modeling or if specific message models/ICD stubs required (answer not provided). Original Q1-Q7 renumbered to Q3-Q9 with answers unchanged.
Multi-Core Parallel Processing for Sensor Fusion Architecture
Q&A Changes Summary
New Questions Added:
- Q1 now contains 5 sub-questions covering: facility clearance requirements for uncleared small businesses, weighting of tactical-aircraft experience vs. architecture quality, serial baseline expectations, prescriptive nature of task decomposition (spatial alignment, temporal correlation, attribute fusion), and proof of track integrity in simulation.
Key Clarifications:
- Facility clearance: Uncleared small businesses with credible sponsorship path are viable offerors; current clearance not required at award.
- Baseline: Establishing the serial baseline is part of Phase I work (not pre-provided).
- Task decomposition: The named sub-tasks are examples, not prescriptive requirements.
- Track integrity proof: Simulation-based evidence of no fused track data loss is acceptable for Phase I.
Renumbered: Previous Q6 (synthetic data availability) is now Q7; all other Q&As shifted accordingly but with no substantive answer changes.
Multi-Core Parallel Processing for Sensor Fusion Architecture
Q&A Updates:
Five previously unanswered questions now have government responses:
- Q1 (Data Sources): Recommends 2-3 sensors for Phase I
- Q2 (New Work): Confirmed government has not begun this work
- Q3 (Latency): No set minimum latency standard required
- Q4 (Determinism): Asynchronous track-state reconciliation acceptable if minimal data/correlation loss
- Q5 (7 sub-questions): Performers may use synthetic multimodal scenarios, desktop computers for modeling, off-the-shelf hardware (CPU/GPU/FPGA), and representative baselines for Phase I proof-of-concept; success measured by latency/throughput/track loss/correlation accuracy comparison; Phase II hardware-in-the-loop simulation testing under review
Q6 remains unanswered regarding synthetic CCA mission data availability.
Multi-Core Parallel Processing for Sensor Fusion Architecture
Added 5 new Q&As (Q1-Q5) covering: minimum data sources, government prior work, latency standards, deterministic vs. asynchronous fusion requirements, and Phase I testing parameters (scenario flexibility, baseline approach, success criteria, hardware options, processor selection, test data). Q6 restates original Q1 on synthetic data availability.
Multi-Core Parallel Processing for Sensor Fusion Architecture
Status changed from Pre-Release to Open
Multi-Core Parallel Processing for Sensor Fusion Architecture
Applicants need to clarify whether they'll receive representative CCA mission data or must develop their own synthetic dataset for Phase I feasibility demonstrations, which affects project planning and resource allocation.
Multi-Core Parallel Processing for Sensor Fusion Architecture
New opportunity: Multi-Core Parallel Processing for Sensor Fusion Architecture
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