RallyPropRallyProp.ai

This solicitation closed on September 23, 2026

View current Department of Defense opportunities →
DON26BZ05-NV077ClosedSBIR

Multi-Core Parallel Processing for Sensor Fusion Architecture

Department of DefenseNAVY

AI Overview

This RFP seeks development of a multi-core parallel processing sensor fusion architecture to eliminate data loss and reduce latency in target tracking for manned and autonomous systems. The modular, platform-agnostic design must integrate multiple sensor types while maintaining real-time performance and compatibility with fifth-generation platforms.

This summary is AI-generated from the official solicitation.

Key Details

Agency
Department of Defense
Funding Amount
—
Release Date
August 5, 2026
Due Date
September 23, 2026 (Closed)

Official Description

The enhancement of target tracking, situational awareness, and decision-making in manned and autonomous systems is accomplished by fusing data from multiple sensors (homogeneous and heterogeneous). There are many complex issues within the implementation of sensor fusion, including, but not limited to, process latency, overprocessing of redundant data, and the inherent serial nature of current fusion architecture. To alleviate these issues, a prioritization ranking system is implemented to proces...

View on official source

Change History

Status ChangedSep 23, 2026 at 4:02 PM

Informational change · Status

Multi-Core Parallel Processing for Sensor Fusion Architecture

Status changed from status: Open to status: Closed.

Q&A UpdatedSep 18, 2026 at 5:02 PM

Informational change · Description

Multi-Core Parallel Processing for Sensor Fusion Architecture

Description information changed.

Q&A UpdatedSep 14, 2026 at 1:01 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Key Change:

Q3 received a comprehensive new answer clarifying five critical points: (1) Secret-level facility clearance not required at Phase I award; uncleared firms with sponsorship path are viable; (2) evaluation is holistic—strong architecture/simulation rigor is primary, not just domain experience; (3) establishing serial baseline is Phase I scope, not government-furnished; (4) sub-task decomposition is illustrative, not prescriptive; (5) track integrity proof via deterministic metrics (zero drops, message accounting, latency/throughput bounds, association accuracy).

Q&A UpdatedSep 10, 2026 at 4:01 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Changes to Q&A:

Added 2 new questions: Q1 asking if topic supports chip development (answer not provided), and Q2 asking if synthetic multi-sensor track/report streams are acceptable for adapter modeling or if specific message models/ICD stubs required (answer not provided). Original Q1-Q7 renumbered to Q3-Q9 with answers unchanged.

Q&A UpdatedSep 3, 2026 at 6:01 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Q&A Changes Summary

New Questions Added:

  • Q1 now contains 5 sub-questions covering: facility clearance requirements for uncleared small businesses, weighting of tactical-aircraft experience vs. architecture quality, serial baseline expectations, prescriptive nature of task decomposition (spatial alignment, temporal correlation, attribute fusion), and proof of track integrity in simulation.

Key Clarifications:

  • Facility clearance: Uncleared small businesses with credible sponsorship path are viable offerors; current clearance not required at award.
  • Baseline: Establishing the serial baseline is part of Phase I work (not pre-provided).
  • Task decomposition: The named sub-tasks are examples, not prescriptive requirements.
  • Track integrity proof: Simulation-based evidence of no fused track data loss is acceptable for Phase I.

Renumbered: Previous Q6 (synthetic data availability) is now Q7; all other Q&As shifted accordingly but with no substantive answer changes.

Q&A UpdatedSep 1, 2026 at 1:01 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Q&A Updates:

Five previously unanswered questions now have government responses:

  • Q1 (Data Sources): Recommends 2-3 sensors for Phase I
  • Q2 (New Work): Confirmed government has not begun this work
  • Q3 (Latency): No set minimum latency standard required
  • Q4 (Determinism): Asynchronous track-state reconciliation acceptable if minimal data/correlation loss
  • Q5 (7 sub-questions): Performers may use synthetic multimodal scenarios, desktop computers for modeling, off-the-shelf hardware (CPU/GPU/FPGA), and representative baselines for Phase I proof-of-concept; success measured by latency/throughput/track loss/correlation accuracy comparison; Phase II hardware-in-the-loop simulation testing under review

Q6 remains unanswered regarding synthetic CCA mission data availability.

Q&A UpdatedAug 27, 2026 at 6:01 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Added 5 new Q&As (Q1-Q5) covering: minimum data sources, government prior work, latency standards, deterministic vs. asynchronous fusion requirements, and Phase I testing parameters (scenario flexibility, baseline approach, success criteria, hardware options, processor selection, test data). Q6 restates original Q1 on synthetic data availability.

Status ChangedAug 26, 2026 at 2:02 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Status changed from Pre-Release to Open

Q&A UpdatedAug 10, 2026 at 6:04 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

Applicants need to clarify whether they'll receive representative CCA mission data or must develop their own synthetic dataset for Phase I feasibility demonstrations, which affects project planning and resource allocation.

Opportunity AddedAug 5, 2026 at 12:02 PM

Multi-Core Parallel Processing for Sensor Fusion Architecture

New opportunity: Multi-Core Parallel Processing for Sensor Fusion Architecture

Similar Opportunities

Get Alerts for Opportunities Like This

RallyProp monitors thousands of funding sources and sends instant alerts when opportunities match your technology and capabilities.

Start Free Trial